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Journal Articles

2019

  1. Takao Kihara, Tomoya Takahashi, and Tsutomu Yoshimura, “Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers“, IEEE Transactions on Circuits and Systems-I: Regular Paper, Vol. 66, No. 6, pp. 2007-2016, June 2019.
    DOI: 10.1109/TCSI.2019.2903650

2016

  1. Tsutomu Yoshimura and Takao Kihara, “Analysis and Modeling of Response of External Noise in Oscillators“, Analog Integrated Circuits and Signal Processing, Vol. 87, Issue 2, pp. 313-325, May 2016.
  2. Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, and Toshimasa Matsuoka, “A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices“, IEICE Transactions on Electronics, Vol. E99-C, No. 4, pp. 431-439, April 2016.

2015

  1. Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, and Toshimasa Matsuoka, “A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator“, IEICE Transactions on Electronics, Vol. E98-C, No. 12, pp. 1179-1186, Dec. 2015.
  2. Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, and Toshimasa Matsuoka, “A Subthreshold Low-Voltage Low-Phase Noise CMOS LC-VCO with Resistive Biasing“, Circuits and Systems, Vol. 6, No. 5, pp. 136-142, May 2015.
  3. Saichandrateja Radhapuram, Jungnam Bae, Ikkyun Jo, Takao Kihara, and Toshimasa Matsuoka, “A Low-Power CMOS Programmable Frequency Divider with Novel Retiming Scheme“, IEICE Electronics Express, Vol. 12, No. 6, pp. 20141233, March 2015.

2013

  1. Takao Kihara, Tomohiro Sano, Masakazu Mizokami, Yoshikazu Furuta, Mitsuhiko Hokazono, Takaya Maruyama, Tetsuya Heima, and Hisayasu Sato, “A Multiband LTE SAW-less CMOS Transmitter with Source-Follower-Driven Passive Mixers, Envelope-Tracked RF-PGAs, and Marchand Baluns”, IEICE Transactions on Electronics, Vol. E96-C, No. 6, pp. 774-782, Jun. 2013.
    DOI: 10.1587/transele.E96.C.774

2010

  1. Takao Kihara, Toshimasa Matsuoka, and Kenji Taniguchi, “A Transformer Noise-Canceling Ultra-Wideband CMOS Low-Noise Amplifier”, IEICE Transactions on Electronics, Vol. E93-C, No. 2, pp. 187-199, Feb. 2010.
    DOI: 10.1587/transele.E93.C.187
  2. Toshimasa Matsuoka, Jun Wang, Takao Kihara, H. Ham, and Kenji Taniguchi, “Low-Voltage Wireless Analog CMOS Circuits toward 0.5 V Operation”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E93-A, No. 2, pp. 356-366, Feb. 2010.

2009

  1. Fumiaki Yamashita, Toshimasa Matsuoka, Takao Kihara, Isao Takobe, Hae-Ju Park, and Kenji Taniguchi, “Analytical Design of a 0.5V 5GHz CMOS LC-VCO”, IEICE Electronics Express, Vol. 6, No. 14, pp. 1025-1031, July 2009.
  2. Takao Kihara, Park Hae-Ju, Isao Takobe, Fumiaki Yamashita, Toshimasa Matsuoka, and Kenji Taniguchi, “A 0.5 V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier”, IEICE Transactions on Electronics, Vol. E92-C, No. 4, pp. 564-575, Apr. 2009.
    DOI: 10.1587/transele.E92.C.564

2007

  1. Takao Kihara, Gue Chol Kim, Msaru Goto, Keiji Namakura, Yoshiyuki Shimizu, Toshimasa Matsuoka, and Kenji Taniguchi, “Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-A, No. 2, pp. 317-325, Feb. 2007.

2006

  1. Gue Chol Kim, Bunsei Murakami, Masaru Goto, Takao Kihara, Keiji Nakamura, Yoshiyuki Shimizu, Toshimasa Matsuoka,and Kenji Taniguchi, “Small-Signal and Noise Model of FD-SOI MOS Devices for Low Noise Amplifier”, Japanese Journal of Applied Physics, Part 1, Vol. 45, No. 9A, pp. 6872-6877, Sep. 2006.
  2. Gue Chol Kim, Yoshiyuki Shimizu, Bunsei Murakami, Masaru Goto, Keisuke Ueda, Takao Kihara, Toshimasa Matsuoka, and Kenji Taniguchi, “Accurate Small-Signal Modeling of FD-SOI MOSFETs“, IEICE Transactions on Electronics, Vol. E89-C, No. 4, pp. 517-519, Apr. 2006.
  3. Takao Kihara, Guechol Kim, Yoshiyuki Shimizu, Bunsei Murakami, Keisuke Ueda, Masaru Goto, Toshimasa Matsuoka,and Kenji Taniguchi, “Design of CMOS Low-Noise Amplifier Considering Noise and Linearity”, IEICE Transactions on Electronics (Japanese Edition), Vol. J89-C, No. 2, pp. 72-75, Feb. 2006.

Conference Proceedings (Peer-Reviewed)

2021

  1. Takao Kihara, “Digital Background Correction for Channel Mismatch and Third-Order Nonlinearity of TI-ADCs with VCOs”, Proc. 2021 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Penang, Malaysia, Nov. 2021, pp. 113-116.
    DOI: 10.1109/APCCAS51387.2021.9687812
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2020

  1. Yuka Nakamatsu, Takao Kihara, “Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation”, Proc. 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Ha Long Bay, Vietnam, Dec. 2020, pp. 54-57.
    DOI: 10.1109/APCCAS50809.2020.9301704
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2019

  1. Yuma Isobe, Takao Kihara, “First-Order Recursive CIC Filters in Time-Interleaved VCO- Based ADCs for Direct-RF Sampling Receivers”, Proc. 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Bangkok, Thailand, Nov. 2019, pp. 22-25.
    DOI: 10.1109/APCCAS47518.2019.8953087
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  2. Takao Kihara, Keisuke Miyakoshi, and Tsutomu Yoshimura, “Digital Third-Order Nonlinearity Correction for Time-Interleaved A/D Converters with VCOs“, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019, pp. 1-4.
    DOI: 10.1109/ISCAS.2019.8702509
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2018

  1. Yuma Isobe, Takao Kihara, Tsutomu Yoshimura, “A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers“, Proc. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , Chengdu, China, Oct. 2018, pp. 163-166.
    DOI: 10.1109/APCCAS.2018.8605669
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  2. Tokuya Fukuyama, Takao Kihara, Tsunehiro Yoshio, Tsutomu Yoshimura, “A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder“, Proc. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , Chengdu, China, Oct. 2018, pp. 22-25.
    DOI: 10.1109/APCCAS.2018.8605659
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  3. Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura, “Study of Mutual Injection Pulling in a 5-GHz, 0.18-um CMOS Cascaded PLL“, Proc. 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , Chengdu, China, Oct. 2018, pp. 175-178.

2017

  1. Tomoya Takahashi, Takao Kihara, Tsutomu Yoshimura, “Digital Correction of Mismatches in Time-Interleaved ADCs for Digital-RF Receivers“, Proc. 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Batumi, Georgia, Dec. 2017, pp. 9-12.
    DOI: 10.1109/ICECS.2017.8292022
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  2. Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura, “Spur Reduction by Self-injection Loop in a Fractional-N PLL“, Proc. 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS) , Batumi, Georgia, Dec. 2017, pp. 260-263.
  3. Tsunehiro Yoshio, Takao Kihara, Tsutomu Yoshimura, “A 0.55 V Back-Gate Controlled Ring VCO for ADCs in 65 nm SOTB CMOS“, Proc. 2017 IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur, Malaysia, Nov. 2017, pp. 946-948.
    DOI: 10.1109/APMC.2017.8251606
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  4. Takao Kihara, Hiroyuki Yano, and Tsutomu Yoshimura, “Design of Cascaded Integrator-Comb Decimation Filters for Direct-RF Sampling Receivers“, Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA, May 2017, pp. 1-4.
    DOI: 10.1109/ISCAS.2017.8050937
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2016

  1. Takao Kihara, Shigesato Matsuda, and Tsutomu Yoshimura, “Analysis and Design of Differential LNAs with On-Chip Transformers in 65-nm CMOS Technology“, Proc. 14th IEEE International NEW Circuits And Systems Conference (NEWCAS), Vancouver, Canada, June 2016, pp. 1-4.
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  2. Naohiro Fujii, Shuei Morishita, Takao Kihara, and Tsutomu Yoshimura, “A 2.6GHz Subharmonically Injection-Locked PLL with Low-Spur and Wide-Lock-Range Injection” , Pro. 14th IEEE International NEW Circuits And Systems Conference (NEWCAS), Vancouver, Canada, June 2016, pp. 1-4.

2015

  1. Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, and Toshimasa Matsuoka, “A Low-Voltage Design of Controller-Based ADPLL for Implantable Biomedical Devices“, in Proc. IEEE Biomedical Circuits and System Conference (BioCAS), Atlanta, USA, Oct. 2015, pp. 1-4.
  2. Jungnam Bae, Saichandrateja Radhapuram, Ikkyun Jo, Takao Kihara, and Toshimasa Matsuoka, “A Low-Voltage Design of Digitally-Controlled Oscillator Based on the gm/ID Methodology“, in Proc. IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), Sendai, Japan, Aug. 2015, pp. 187-189.
  3. Shuei Morishita, Shinji Shimizu, Takao Kihara, and Tsutomu Yoshimura, “Subharmonically Injection-Locked PLL with Variable Pulse-Width Injections“, in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May 2015, pp. 557-560.

2012

  1. Takao Kihara, Tomohiro Sano, Masakazu Mizokami, Yoshikazu Furuta, Takahiro Nakamura, Mitsuhiko Hokazono, Takaya Maruyama, Kenji Toyota, Koji Maeda, Yukinori Akamine, Taizo Yamawaki, Tetsuya Heima, Kazuaki Hori, and Hisayasu Sato, “A Multiband LTE SAW-less CMOS Transmitter with Source-Follower-Drived Passive Mixers, Envelope-Tracked RF-PGAs, and Marchand Baluns”, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest Papers, Montreal, Canada, Jun. 2012, pp. 399-402.
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2008

  1. Takao Kihara, Toshimasa Matsuoka, and Kenji Taniguchi, “A 1.0 V, 2.5 mW, Transformer Noise-Canceling UWB CMOS LNA“, in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest Papers, Atlanta, USA, Jun. 2008, pp. 493-496.
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  2. Takao Kihara, Hae-Ju Park, Isao Takobe, Fumiaki Yamashita, Toshimasa Matsuoka, and Kenji Taniguchi, “A 0.5 V Area-Efficient Transformer Folded-Cascode Low-Noise Amplifier in 90 nm CMOS“, in Proc. IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), Grenoble, France, Jun. 2008, pp. 21-24.

Patents

  1. Masakazu Mizokami and Takao Kihara, “Semiconductor device“, US 10,305,533, May 28, 2019.
    DOI (Related paper): 10.1109/ISSCC.2015.7063015
  2. Takao Kihara, “Semiconductor device including spiral shape inductor and horseshoe shape inductor“, US 9,577,698, Feb. 21, 2017.
  3. Takao Kihara and Tomohiro Sano, “Semiconductor device and adjustment method of filter circuit“, US 9,190,977, Nov. 17, 2005.
  4. Takahiro Nakamura, Taizo Yamawaki, Takayasu Norimatsu, and Takao Kihara, “Quadrature modulator and semiconductor integrated circuit with it built-in“, US 8,299,865, Oct. 30, 2012.